TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 109

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TMPM382FSFG

Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM382FSFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
7 Exceptions
CGIMCGD
0x4004_022C
7.6.3.4 CG Interrupt Mode Control Register D
This resister set the clearing standby request active level of external interrupt INTC~INTF.
(Note1)
(Note2)
(Note3)
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Refer to EMSTxx bit to know the active condition which is used for clearing
standby.
Please specify the bit for the edge first and then specify the bit for the <INTxEN>.
Setting them simultaneously is prohibited.
Bit[22:20][14:12][6:4] for TMPM382.
INTC to INTE is for TMPM380 Only. Write "0" to Bit[16][8][0] and "010" to
“0” is read
“0” is read
“0” is read
“0” is read
15
23
31
7
R
R
R
R
0
0
0
0
Active state setting of INTC standby
clear request. (101~111: setting
prohibited)
Active state setting of INTD standby
clear request. (101~111: setting
prohibited)
Active state setting of INTE standby
clear request. (101~111: setting
prohibited)
Active state setting of INTF standby
clear request. (101~111: setting
prohibited)
TMPM380/M382 - 54 / 59 -
EMCGC2 EMCGC1 EMCGC0
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCGD2 EMCGD1 EMCGD0
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCGE2 EMCGE1 EMCGE0 EMSTE1 EMSTE0
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCGF2
14
22
30
6
0
0
0
0
EMCGF1
R/W
R/W
R/W
R/W
13
21
29
5
1
1
1
1
EMCGF0 EMSTF1 EMSTF0
12
20
28
4
0
0
0
0
standby clear request
standby clear request
standby clear request
standby clear request
Active state of INTC
Active state of INTD
Active state of INTE
Active state of INTF
00: -
01: Rising edge
10: Falling edge
11: Both edges
00: -
01: Rising edge
10: Falling edge
11: Both edges
00: -
01: Rising edge
10: Falling edge
11: Both edges
00: -
01: Rising edge
10: Falling edge
11: Both edges
EMSTC
EMSTD
19
27
11
3
1
1
0
0
0
0
R
R
R
R
EMSTC
EMSTD
10
18
26
2
0
0
0
0
0
0
Reads as
undefined.
Reads as
undefined.
“0” is read
Reads as
undefined.
Undefined
Undefined
Undefined
Undefined
TMPM380/M382
17
25
1
R
9
R
R
R
INTC clear
input
0: Disable
1: Enable
INTD clear
input
0: Disable
1: Enable
INTE clear
input
0: Disable
1: Enable
INTF clear
input
0: Disable
1: Enable
INTCEN
INTEEN
INTDEN
INTFEN
R/W
R/W
R/W
R/W
16
24
0
8
0
0
0
0

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