TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 196

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

9 16-bit Timer/Event Counters (TMRBs)
TBxCR
(0x4001_0xx8)
<I2TB>
<TBSYNC>
<TBWBF>
9.6.5
(note2)
(note1)
becomes possible.
output.
Taking the synchronization of the start between timers by using the timer synchronous mode
It divides into two blocks of TMRB0,1,2,3 and TMRB4,5,6,7.
When I set <TBSYNC>=“1", I will not start in timer start TBxRUN<TBPRUN, TBRUN>=”1, 1” of
each ch, and start synchronizing with TMRB0 and TMRB4.
Synchronous Timer Mode
It is possible to apply it to the drive such as motors by using the synchronous mode by the PPG
Please set things except a synchronous output mode to TBxCR<TBSYNC>=“0".
before it starts by TMRB0,4.
Other timers do not start until TMRB0,4 start when a synchronous output mode is set.
bit Symbol
Read/Write
After reset
Please set the timer that outputs the same period to TBxRUN<TBPRUN and TBRUN>=“1,1"
Function
The synchronous mode is switched by TBxCR<TBSYNC >.
Please always set the TBSYNC bit to "0" about TMRB0,4 to have decided a synchronous
start.
Please set the TBSYNC bit to "1" about the timer begun subordinating it.
In the IDLE mode, it is possible to select it.
The timer output can be synchronized with each 4ch.
A double buffer of the timer register is controlled.
<TBSYNC>=“0” : It operates according to the timing of each ch of the timer.
<TBSYNC>=“1” : It outputs it synchronously.
Double
Buffer
0: Disabled
1: Enabled
Synchronous Timer Output Control Register (x=0~7)
TBWBF
R/W
7
0
Write “0” Sync. mode
R/W
6
0
TMPM380/M382 - 30 / 34 -
select
0:Asyunc
1:Syunc
TBSYNC
R/W
5
0
“0” is read During IDLE
4
R
0
mode
0:Stop
1:Operation
I2TB
R/W
3
0
“0” is read
2
R
0
External
Trigger
0: Rising
1: Falling
TRGSEL
TMPM380/M382
edge
edge
R/W
1
0
Counter
Start
0: Software
1: External
CSSEL
start
trigger
R/W
0
0