TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 212

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

10 16-bit Multi-purpose Timers (MPTs)
＜MTTBFF0C1:0＞:Controls the timer flip-flop.
＜MTTBE0T1＞:Reverses the timer flip-flop when the up-counter matches the timer register 0 (MTnRG0).
＜MTTBE1T1＞:Reverses the timer flip-flop when the up-counter matches the timer register 1 (MTnRG1).
＜MTTBC0T1＞:Reverses the timer flip-flop when the up-counter value is taken into the capture register 0
10.4.1.6
Read/Write
Read/Write
Read/Write
bit Symbol
Read/Write
After reset
Function
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
10 : Clears MTnFF0 to “0”.
11 :Don’t care
00 : Reverses the value of MTnFF0
01 : Sets MTnFF0 to “1”.
0: MTnFF0
1: MTnFF0
0: MTnFF0
1: MTnFF0
0: MTnFF0
1: MTnFF0
(MTnCP0).
MPT flip-flop control register <Timer mode>
31
23
15
R
R
R
0
0
0
7
1
-
-
-
not reverse
reverse
not reverse
reverse
not reverse
reverse
-
“11” is read.
R
30
22
14
R
R
R
6
1
0
0
0
-
-
-
-
TMPM380/M382 - 12 / 87 -
When the
up-counter
value is
taken into
MTnCP1
MTnFF0 reverse trigger control
MTTBC1T1
0: Disable trigger
1: Enable trigger
29
21
13
R
R
R
0
0
0
5
0
-
-
-
MTnTBFFCR (n=0, 1, 2)
When the
up-counter
value is
taken into
MTnCP0
MTTBC0T1
28
20
12
R
R
R
0
0
0
4
0
-
-
-
“0” is read
“0” is read
“0” is read
R/W
When the
up-counter
matches
MTnRG1
MTTBE1T1
27
19
11
R
R
R
0
0
0
3
0
-
-
-
When the
up-counter
matches
MTnRG0
MTTBE0T1
26
18
10
R
R
R
0
0
0
2
0
-
-
-
MTnFF0 control
00: Invert
01: Set
10: Clear
11: Don't care
MTTBFF0C1 MTTBFF0C0
* This is always read
as “11.”
25
17
R
R
R
0
0
9
0
1
0
-
-
-
R/W
TMPM380/M382
24
16
R
R
R
0
0
8
0
0
0
-
-
-