TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 239

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

10.5.5
10.5.6
10.5.7
10.5.8
10.5.9 Timer Flip-flop (MT0FF0)
and MT0CP1 capture registers.
<MTTBCPM[1:0]>.
register; specifically, MTUC0 values are taken into the MT0CP0 capture register each time “0” is
written to MT0TBMOD<MTTBCP>. To use this capability, the prescaler must be running
(MT0RUN<MTPRUN> = “1”).
the capture register, use a 16-bit data transfer instruction or read in the order of low-order bits
followed by high-order bits.
be captured by reading the MTUC0 registers.
up-counter with set values of the MT0RG0 and MT0RG1 timer registers. If a match is detected,
INTMTTB00 and INTMTTB01 are generated.
signal to the capture registers.
MT0TBFFCR<MTTBC1T1, MTTBC0T1, MTTBE1T1, MTTBE0T1>.
Capture Control
Capture Registers (MT0CP0, MT0CP1)
Up-counter capture register (MT0UC)
Comparators (MT0CP0, MT0CP1)
This is a circuit that controls the timing to latch MTUC0 up-counter values into the MT0CP0
The value of MT0FF0 becomes undefined after a reset. The flip-flop can be reversed by
Software can also be used to capture values from the MTUC0 up-counter into the capture
These are 16-bit registers for latching values from the MTUC0 up-counter. To read data from
Other than the capturing functions shown above, the current count value of the MTUC0 can
These are 16-bit comparators for detecting a match by comparing set values of the MTUC0
The timer flip-flop (MT0FF0) is reversed by a match signal from the comparator and a latch
Register setting
data transfer instruction written twice in the order of low-order 8 bits followed by high-order
8 bits can be used.
<MTTBWBF> = “0,” the same value is written to MT0RG0, MT0RG1 and each register
buffer; if <MTTBWBF> = “1” the value is only written to each register buffer. Therefore, in
order to write an initial value to the timer register, the register buffers must be set to
“disable”. Then set <MTTBWBF> = “1”and write the following data to the register.
1) When not using double-buffering
To write data to the timer registers, either a 2-byte data transfer instruction or a 1-byte
2) When using double-buffering
MT0RG0/ MT0RG1 and the register buffers are assigned to the same address. If
TMPM380/M382 - 39 / 87 -
It can be enabled or disabled to reverse by setting the
The timing to latch data is specified by MT0TBMOD
TMPM380/M382