TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 246

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

10 16-bit Multi-purpose Timers (MPTs)
10.6.4
10.6.5
Figure 10-5 Count-up/ count clearing when source clock φT1, φT2 or φT4 is selected.
If the MT0IGR4 matches with up-counter (MTUC0), counter is cleared and data is updated on next
period. At this timing, data is transferred to timer register (MT0IGRG4) from register buffer 4.
comparator detects a match between a values set in these timer registers, it outputs a match
detection signal. Timer registers (MT0RG0, MT0RG1, MT0IGRG2, MT0IGRG3) are the
double-buffered configuration and are paired of register buffer. If MT0IGRG4 matches with
up-counter (MTUC0), counter is cleared at the same time data is updated. At this time, data is
transferred to timer register (MT0IGRG2 or 3) from register buffer 2 or 3.
Period Setup register is a double-buffered configuration register which sets PPG output periods.
Period Setup Register (MT0IGRG4)
Timer Registers (MT0RG0, MT0RG1, MT0IGRG2, MT0IGRG3)
In the IGBT mode, MT0RG0 and 1 are always doubled-buffered configuration.
Timer registers are registers for setting values to compare with up-counter values. If the
Write and read operation of timer register (MT0RG0, MT0RG1, MT0IGR2, MT0IGRG3) and
MT0IGRG2, MT0IGRG3) and period setup register (MT0IGRG4).
with up-counter (MTUC0), counter is cleared at the same time data is updated.
value of register buffer cannot be read.
Note)
2) Other than source clockφT0 is selected
When source clock φT1, φT2 or φT4 is selected, one source clock is required for the
match count and the clear count. Thus a value of period setup is set to M.
1) When timer registers and period setup register are written
When timer is stopping, data can be written into timer register (MT0RG0, MT0RG1,
When timer is in operation, data is latched in each register buffer. If MT0IGRG4 matches
2) When timer registers and period setup register are read
Current value of 16-bit comparator and the target register for comparison to be read. A
period setup register (MT0IGRG4)
Write to this register by unit of 16 bits or 32 bits. Writing in unit of 8 bits is prohibited.
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TMPM380/M382