TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 247

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

10.6.6
10.6.7
10.6.8
10.6.9
10.6.10 Capture Interrupt (INTMTCAP00, INTMTCAP01)
captured by MT0CP0 and MT0CP1 at the rising edge and falling edge of MT0IN pin respectively.
up-counter with set values of the timer registers (MT0RG0, MT0RG1, MT0IGRG2, MT0IGRG3
and MT0IGRG4) to detect a match.
between up-counter and timer register. The initial mode setting of output control signals are
specified with MT0IGOCR<IGPOL0,1>. After reset, these signals are set to “Low”
(MT0IGOCR<IGPOL0,1>=0). If MT0IGOCR<IGPOL0,1> is set to “0”, the initial state is “Low”. If
MT0IGOCR<IGPOL0,1> is set to “1”, the initial state is “High”.
are disabled. When using these signals, set MT0IGOCR<IGOEN0,1>=1.
from the MTUC0 up-counter into the MT0CP0 and MT0CP1 capture registers. The interrupt
setting is specified with a register of CPU.
Capture Control
Capture Registers (MT0CAP0, MT0CAP1)
Comparators (CP0, CP1, CP2, CP3, CP4)
Output Signal Control (MTOUT00, MTOUT01)
By setting to command start mode or trigger capture mode, up-counter values (MTUC0) are
These are registers for latching values from the up-counter (MTUC0).
These are comparators for detecting a match by comparing set values of the MTUC0
Output Signal Control signals (MTOUT00, MTOUT01) are changing by a match detect signal
Output control signals are specified with MT0IGOCR<IGOEN0,1>. After reset, these signals
Interrupts INTMTCAP00 and INTMTCAP01 can be generated at the timing of latching values
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TMPM380/M382