TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 280

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

10 16-bit Multi-purpose Timers (MPTs)
•
EMG Control Register (MTPDnEMGCR)
<EMGEN>: EMG protection circuit enable/disable
<EMGRS>: EMG protection release
Bit2: write “0”
<EMGMD>: EMG protection mode select
<INHEN>: Tool break enable/disable
<EMGCNT>: EMG input detection time
Read/Write
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
After reset
0: Disable
1: Enable
circuit is enabled.
the EMGEN bit to 0.
0: -
1: Release protection
EMG protection can be released by setting the MTPDnMDOUT register to 0 and then setting the
EMGRS bit
to 1.
This bit is always read as 0.
00: PWM output control disabled / Port output = All phases High-Z
01: All upper phases ON, all lower phases OFF / Port output = Lower phases High-Z
10: All upper phases OFF, all lower phases ON / Port output = Upper phases High-Z
11: All phases OFF / Port output = All phases High-Z
emergency.
0: Disable
1: Enable
the initial state, tool breaks are enabled.
0 to 15 (When <EMGCNT=0, the noise filter is bypassed.)
* ON = PWM output (no output control), OFF = Low [when <POLL>,<POLH>=1 (active high)]
The EMG protection circuit is enabled by setting this bit to 1. In the initial state, the EMG protection
To disable this circuit, write 5A and A5 in this order to the MTPDnEMGREL register and then clear
This field controls PWM output and port output of the upper and lower phases in case of an
This bit selects whether or not to stop the PMD when the PMD stop signal is input from the tool. In
* Be sure to write 0 to both the upper bits [10:8] and lower bits [5:0].
* Before releasing EMG protection, make sure that the EMG input has returned to high.
EMGCNT×16/fsys (resolution: 400[ns] at 40 MHz)
R→0
R→0
R→0
R→0
0x4005 0434, 0x4005 04B4
31
23
15
0
0
0
7
0
-
-
-
-
R→0
R→0
R→0
R→0
30
22
14
0
0
0
6
0
-
-
-
-
TMPM380/M382 - 80 / 87 -
INHEN
R→0
R→0
R→0
R/W
29
21
13
0
0
0
5
1
-
-
-
R→0
R→0
R→0
28
20
12
0
0
0
4
1
-
-
-
EMGMD
R/W
R→0
R→0
27
19
11
0
0
0
1
3
-
-
R→0
R→0
R/W
26
18
10
0
0
0
0
2
-
-
-
EMGCNT
R/W
EMGRS
R→0
R→0
25
17
W
0
0
9
0
0
1
-
-
TMPM380/M382
EMGEN
R→0
R→0
R/W
24
16
0
0
8
0
0
1
-
-