TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 285

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

000:Trigger output disabled
001:Trigger output on down-count match
010:Trigger output on up-count match
011:Trigger output on up-/down-count match
100:Trigger output at PWM carrier peak
101:Trigger output at PWM carrier bottom
110:Trigger output at PWM carrier peak/bottom
111:Trigger output disabled
* It is prohibited to set MTPDnTRGCMPx to 0 or the MTPDnMDPRD value.
* To load the data in MTPDnTRGCMP0 and MTPDnTRGCMP1 to the second buffers, select the bus
* Do not write to these registers in byte units. If the upper 8 bits [15:8] and the lower 8 bits [7:0] are
* When MTPDnTRGCMPx is set to 0x0001, no trigger output is made only in the first cycle after
output. When MTPDnTRGCMPx is read, the value in the first buffer of the double buffers (data set via
the bus) is returned.
Update Timing of the Trigger Compare Register (MTPDnTRGCMPx)
written to MTPDnTRGCMPx is loaded to the second buffer depends on the setting of
MTPDnTRGCR<TRGxMD>. When MTPDnTRGCR<TRGxBE> is set to 1, data written to
MTPDnTRGCMPx is immediately loaded to the second buffer.
When the PMD counter value (MDCNT) matches the value set in MTPDnTRGCMPx, PMDTRG is
The Trigger Compare Register (MTPDnTRGCMPx) is double-buffered. The timing at which the data
Table 10-10 TRGCMPx Buffer Update Timing according to Trigger Output Mode Setting
MTPDnTRGCMPx should be set in a range of 1 to [MDPRD set value – 1].
mode (default) by setting MTPDnMODESEL<MDSEL> to 0.
written separately, operation cannot be guaranteed.
PWM start (MTPDnMDEN<PWMEN>1).
TRGxMD
TMPM380/M382 - 85 / 87 -
Always updated
Updated when PWM counter equals MDPRD (PWM carrier peak)
Updated when PWM counter equals 1 (PWM carrier bottom)
Updated when PWM counter equals 1 or MDPRD
Always updated
(PWM carrier peak/bottom)
MTUFx Update Timing
TMPM380/M382