TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 296

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

flag that is set when an AD conversion result is stored in the ADREGn register and is cleared when the
low-order byte of ADREGn is read. Bit 1 (OVRn) is an overrun flag. This flag is set when a new AD
conversion result is stored before the low-order byte of ADREGn is read and is cleared when the
low-order byte of ADREGn is read.
0x4003_0020
0x4003_0024
ADREG0
ADREG1
The ADREGn (n = 0 to 11) register is used to store the result of an AD conversion. Bit 0 (ADRnRF) is a
There are twelve ADREGn registers, which are all functionally equivalent.
11.3.4 AD Conversion Result Registers
11.3.4.1
Read/Write
Read/Write
Read/Write
Read/Write
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
ADREG0
Function
Function
ADREG1
Function
Function
ADREG0 to ADREG11
Bits 0 to 3 of an AD conversion result
Bits 4 to 11 of an AD conversion result
Bits 0 to 3 of an AD conversion result
Bits 4 to 11 of an AD conversion result
ADR003
ADR103
ADR011
ADR111
15
15
R
R
R
R
7
0
0
7
0
0
ADR002
ADR102
ADR010
ADR110
14
14
R
R
R
R
0
0
0
0
6
6
TMPM380/M382 - 9 / 39 -
ADR001
ADR009
ADR101
ADR109
13
13
R
R
R
R
5
0
0
5
0
0
ADR000
ADR008
ADR100
ADR108
12
12
R
R
R
R
4
0
0
4
0
0
as 0.
as 0.
Always read
Always read
ADR007
ADR107
11
11
R
R
R
R
3
0
0
3
0
0
-
-
Always read
as 0.
Always read
as 0.
ADR006
ADR106
10
10
R
R
R
R
2
0
0
2
0
0
-
-
Overrun flag
0: No
overrun
occurred
1: Overrun
occurred
Overrun flag
0: No
overrun
occurred
1: Overrun
occurred
TMPM380/M382
ADR005
ADR105
OVR0
OVR0
R
R
R
R
1
0
9
0
1
0
9
0
AD conversion
result store
flag
0: No result
stored
1: Result
stored
AD conversion
result store
flag
0: No result
stored
1: Result
stored
ADR0RF
ADR1RF
ADR004
ADR104
R
R
R
R
0
0
8
0
0
0
8
0