TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 365

no-image

TMPM382FSFG

Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM382FSFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
13 Serial channel (UART/SIO)
13.3.9 Transmit Counter
13.3.10 Transmit Control Unit
I/O interface mode:
Asynchronous (UART) mode:
TXDCLK
The transmit counter is a 4-bit binary counter used in the asynchronous communication
(UART) mode. It is counted by SIOCLK as in the case of the receive counter and generates
a transmit clock (TXDCLK) on every 16th clock pulse.
SIOCLK
When the CPU writes data to the transmit buffer, data transmission is initiated on the
rising edge of the next TXDCLK and the transmit shift clock (TXDSFT) is also generated.
In the SCLK output mode with SC0CR <IOC> set to “0,” each bit of data in the transmit
buffer is output to the TXD0 pin on the falling edge of the shift clock output from the
SCLK0 pin.
In the SCLK input mode with SC0CR <IOC> set to “1,” each bit of data in the transmit
buffer is output to the TXD0 pin on the rising or falling edge of the input SCLK signal
according to the SC0CR <SCLKS> setting.
15
16
1
Fig 13-5 Transmit Clock Generation
2
TMPM380/M382 - 16 / 52 -
3
4
5
6
7
8
9
10
11
12
13
14
TMPM380/M382
15
16
1
2

Related parts for TMPM382FSFG