TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 367

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

13 Serial channel (UART/SIO)
13.3.11 Transmit Buffer
The transmit buffer (SC0BUF) is in a dual structure. The double buffering function may be
enabled or disabled by setting the double buffer control bit <WBUF> in serial mode control
register 2 (SC0MOD2). If double buffering is enabled, data written to Transmit Buffer
(SCOBUF) is moved to Transmit shift register.
If the transmit FIFO has been disabled (SCOFCNF <CNFG> = 0 or 1 and SC0MOD1＜
FDPX1:0＞＝01), the INTTX0 interrupt is generated at the same time and the transmit
buffer empty flag <TBEMP> of SC0MOD2 is set to “1.” This flag indicates that Transmit
Buffer is now empty and that the next transmit data can be written. When the next data is
written to Transmit Buffer, the <TBEMP> flag is cleared to “0.”
If the transmit FIFO has been enabled (SCNFCNF <CNFG> = 1 and SC0MOD1＜FDPX1:0
＞＝10/11), any data in the transmit FIFO is moved to the Transmit Buffer and <TBEMP>
flag is immediately cleared to “0.” The CPU writes data to Transmit Buffer or to the transmit
FIFO.
If the transmit FIFO is disabled in the I/O interface SCLK input mode and if no data is set in
Transmit Buffer before the next frame clock input, which occurs upon completion of data
transmission from Transmit shift register, an under-run error occurs and a serial control
register (SC0CR) <PERR> parity/under-run flag is set.
If the transmit FIFO is enabled in the I/O interface SCLK input mode, when data
transmission from Transmit shift register is completed, the Transmit Buffer data is moved to
Transmit shift register and any data in transmit FIFO is moved to Transmit Buffer at the
same time.
If the transmit FIFO is disabled in the I/O interface SCLK output mode, when data in
Transmit Buffer is moved to Transmit shift register and the data transmission is completed,
the SCLK output stops. So, no under-run errors can be generated.
If the transmit FIFO is enabled in the I/O interface SCLK output mode, the SCLK output
stops upon completion of data transmission from Transmit shift register if there is no valid
data in the transmit FIFO.
If double buffering is disabled, the CPU writes data only to Transmit shift register and the
transmit interrupt INTTX0 is generated upon completion of data transmission.
If handshaking with the other side is necessary, set the double buffer control bit <WBUF> to
“0” (disable) to disable Transmit Buffer; any setting for the transmit FIFO should not be
performed.
Note) In the I/O interface SCLK output mode, the SC0CR <PEER> flag is
insignificant. In this case, the operation is undefined. Therefore, to switch
from the SCLK output mode to another mode, SC0CR must be read in
advance to initialize the flag.
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TMPM380/M382