TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 370

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TMPM382FSFG

Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM382FSFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Transmit FIFO Forth stage
I/O interface mode with SCLK input (normal mode):
Transmit shift register
SC0MOD0<TXE>
SC0MOD2<TBEMP>
Transmit interrupt (INTTX0)
Transmit buffer
The following example describes the case a 4-byte data stream is transmitted:
In this condition, data transmission can be initiated along with the input clock by setting the
transfer mode to half duplex, writing 5 bytes of data to the transmit FIFO, and setting the
<TXE> bit to “1.” When the last transmit data is moved to the transmit buffer, the transmit
FIFO interrupt is generated.
SCxMOD1<6:5> 10 : Transfer mode is set to half duplex.
SCxFCNF<4:0> 01011 : Transmission is automatically disabled if FIFO becomes empty.
SCxTFC<1:0> 00 : Sets the interrupt generation fill level to "0".
SCxTFC<7:6> 11 : Clears receive FIFO and sets the condition of interrupt generation.
Second stage
Third stage
First stage
Fig 13-9 Transmit FIFO Operation(2)
TMPM380/M382 - 21 / 52 -
DATA5
DATA4
DATA3
DATA2
DATA1
The number of bytes to be used in the receive FIFO is the same
as the interrupt generation fill level.
DATA5
DATA2
DATA3
DATA4
DATA1
DATA5
DATA4
DATA3
DATA2
DATA5
DATA4
DATA3
DATA5
DATA4
TMPM380/M382
DATA5

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