TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 373

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

13 Serial channel (UART/SIO)
13.3.16 Direction of Data Transfer
13.3.17 Stop Bit Length
13.3.18 Status Flag
In the I/O interface mode, the direction of data transfer can be switched between “MSB first”
and “LSB first” by the data transfer direction setting bit <DRCHG> of the SC0MOD2 serial
mode control register 2. Don't switch the direction when data is being transferred.
In the UART transmission mode, the stop bit length can be set to either 1 or 2 bits by bit 4
<SBLEN> of the SC0MOD2 register. The length of the STOP bit data is determined as
one-bit when it is received regardless of the setting of this bit.
If the double buffer function is enabled (SC0MOD2 <WBUF> = “1”), the bit 6 flag <RBFLL>
of the SC0MOD2 register indicates the condition of receive buffer full. When one frame of
data has been received and transferred from shift registers to buffers, this bit is set to “1” to
show that buffers are full (data is stored in the buffers). When the receive buffer is read by
CPU/DMAC, it is cleared to “0.” If <WBUF> is set to “0,” this bit is insignificant and must not
be used as a status flag. When double buffering is enabled (SC0MOD2 <WBUF> = “1”), the
bit 7 flag <TBEMP> of the SC0MOD2 register indicates that Transmit Buffer is empty. When
data is moved from Transmit Buffer to Transmit shift register, this bit is set to “1” indicating
that Transmit Buffer is now empty. When data is set to the transmit buffer by CPU/DMAC,
the bit is cleared to “0.” If <WBUF> is set to “0,” this bit is insignificant and must not be used
as a status flag.
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