TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 392

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TMPM382FSFG

Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM382FSFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Receive data
write timing
Receive data
write timing
Receive data
write timing
(INTRX0 interrupt request)
(INTRX0 Interrupt request)
(INTRX0 Interrupt request)
RBFULL
RBFULL
SCLK0 output
SCLK0 output
SCLK0 output
RXD0
RXD0
RXD0
<WBUF>=“1” (if double buffering is enabled and data cannot be read from buffer)
Fig 13-12 Receive Operation in the I/O Interface Mode (SCLK0 Output Mode)
<WBUF>=“1” (if double buffering is enabled and data is read from buffer)
Receiving data
SCLK output mode
bit
bit
In the SCLK output mode, if SC0MOD2 <WBUF> = “0” and receive double buffering is
disabled, a synchronous clock pulse is output from the SCLK0 pin and the next data is
shifted into receive shift register each time the CPU reads received data. When all the
8 bits are received, the INTRX0 interrupt is generated.
The first SCLK output can be started by setting the receive enable bit SC0MOD0
<RXE> to “1.” If the receive double buffering is enabled with SC0MOD2 <WBUF> set
to “1,” the first frame received is moved to receive buffer and receive shift register can
receive the next frame successively. As data is moved from receive shift register to
receive buffer, the receive buffer full flag SC0MOD2 <RBFULL> is set to “1” and the
INTRX0 interrupt is generated.
While data is in receive buffer, if CPU/DMAC cannot read data from receive buffer
before completing reception of the next 8 bits, the INTRX0 interrupt is not generated
and the SCLK0 clock stops. In this state, reading data from receive buffer allows data
in receive shift register to move to receive buffer and thus the INTRX0 interrupt is
generated and data reception resumes.
7
7
<WBUF>=“0” (if double buffering is disabled)
bit 0
bit 0
bit 0
TMPM380/M382 - 43 / 52 -
bit 1
bit 1
bit 1
bit 6
bit 6
bit 6
bit 7
bit 7
bit 7
bit 0
TMPM380/M382
bit 0

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