TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 396

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

TMPM380/M382
SCLK input mode
In the SCLK input mode with SC0MOD2 <WBUF> set to “0” and the transmit double
buffers are disabled (double buffering is always enabled for the receive side), 8-bit
data written in the transmit buffer is output from the TXD0 pin and 8 bits of data is
shifted into the receive buffer when the SCLK input becomes active. The INTTX0
interrupt is generated upon completion of data transmission and the INTRX0 interrupt
is generated at the instant the received data is moved from receive shift register to
receive buffer. Note that transmit data must be written into the transmit buffer before
the SCLK input for the next frame (data must be written before the point A in Fig 13-15).
As double buffering is enabled for data reception, data must be read before completing
reception of the next frame data.
If SC0MOD2 <WBUF> = “1” and double buffering is enabled for both transmission and
reception, the interrupt INTRX0 is generated at the timing Transmit Buffer data is
moved to Transmit shift register after completing data transmission from Transmit shift
register. At the same time, the 8 bits of data received is shifted to shift register, it is
moved to receive buffer, and the INTRX0 interrupt is generated. Upon the SCLK input
for the next frame, transmission from Transmit shift register (in which data has been
moved from Transmit Buffer) is started while receive data is shifted into receive shift
register simultaneously. If data in receive buffer has not been read when the last bit of
the frame is received, an overrun error occurs. Similarly, if there is no data written to
Transmit Buffer when SCLK for the next frame is input, an under-run error occurs.
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