TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 404

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

14.2 Overview of SSP
This LSI contains the SSP with two channels: channels 0, and 1 channels operate in the same way,
only channel 0 is described in the following sections.
The SSP is an interface that enables serial communications with the peripheral devices with three
types of synchronous serial interface functions.
The SSP performs serial-parallel conversion of the data received from a peripheral device. The
transmit path buffers data in the independent 16-bit wide and 8-layered transmit FIFO in the transmit
mode, and the receive path buffers data in the 16-bit wide and 8-layered receive FIFO in receive mode.
Serial data is transmitted via SP0DO and received via SP0DI.
The SSP contains a programmable prescaler to generate the serial output clock SP0CLK from the
input clock fsys. The operation mode, frame format, and data size of the SSP are programmed in the
control registers SSP0CR0 and SSP0CR1.
(1) Clock prescaler
(2) Transmit FIFO
(3) Receive FIFO
When configured as a master, a clock prescaler comprising two free-running serially linked
counters is used to provide the serial output clock SP0CLK.
You can program the clock prescaler through the SSP0CPSR register, to divide fsys by a factor of
2 to 254 in steps of two. Because the least significant bit of the SSP0CPSR register is not used,
division by an odd number is not possible.
The output of the prescaler is further divided by a factor of 1 to 256, which is obtained by adding 1
to the value programmed in the SSP0CR0 control register, to give the master output clock
SP0CLK.
This is a 16-bit wide, 8-layered transmit FIFO buffer, which is shared in master and slave modes.
This is a 16-bit wide 8-layered receive FIFO buffer, which is shared in master and slave modes.
fsys
Bit rate = fsys / (CPSDVSR × (1+SCR))
(Depends on the setting)
Clock initial value
CPSDVSR [7:1]
Clock prescaler
TMPM380/M382 - 3 / 28 -
SSPCLKDIV
(SCR [7:0] + 1)
Divider circuit
Toggle circuit
Clock invert
trigger
SP0CLK
TMPM380/M382