TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 405

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

14 SSP (Synchronous Serial Port)
(4) Interrupt generation logic
interrupt enable (RTIM)
empty flag (RNE)
interrupt (RTINTR)
Four HIGH active interrupts, each of which can be masked separately, are generated. Also,
individual interrupt requests are combined and output as a single integrated interrupt.
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(a) Transmit interrupt
(b) Receive interrupt
(c) Timeout interrupt
counter enable
Receive timeout
Internal down
Receive FIFO
Receive timeout
SP0CLK
The transmit interrupt is asserted when there are four or fewer valid entries in the transmit
FIFO. The transmit interrupt is also generated when the SSP operation is disabled
(SSP0CR1<SSE>=0).
The first transmitted data can be written in the FIFO by using this interrupt.
The receive interrupt is asserted when there are four or more valid entries in the receive
FIFO.
The receive timeout interrupt is asserted when the receive FIFO is not empty and the SSP
has remained idle for a fixed 32-bit period (bit rate). This mechanism ensures that the user is
aware that data is still present in the receive FIFO and requires servicing. This operation
occurs in both master and slave modes. When the timeout interrupt is generated, read all
data from the receive FIFO. Even if all the data is not read, data can be transmitted/received
if the receive FIFO has a free space and the number of data to be transmitted does not
exceed the free space of the receive FIFO. When transfer starts, the timeout interrupt will be
cleared. If data is transmitted/received when the receive FIFO has no free space, the timeout
interrupt will not be cleared and an overrun interrupt will be generated.
Transmit interrupt: Interrupt conditional upon TxFIFO having free space equal to or more
than half its entire capacity.
(Number of valid data items in the TxFIFO ≤ 4)
Receive interrupt: Interrupt conditional upon RxFIFO having valid data equal to or more than
half its entire capacity.
(Number of valid data items in the RxFIFO ≥ 4)
Timeout interrupt: Interrupts indicating that the data in RxFIFO is not read before the timeout
period expires.
Receive overrun interrupt: Conditional interrupts indicating that data is written to RxFIFO
when it is full
When any of the above interrupts is asserted, INTSSP0 is asserted.
TMPM380/M382 - 4 / 28 -
During data transfer
bit rate x 32
TMPM380/M382