TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 406

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

(5) DMA interface
The SSP provides an interface to connect to a DMA controller.
(d) Receive overrun interrupt
(e) Combined interrupt
When the next data (9th data item) is received when the receive FIFO is already full, a
receive overrun interrupt is generated immediately after transfer. The data received after the
receive overrun interrupt is generated (including the 9th data item) will become invalid and
be discarded. However, if data is read from the receive FIFO while the 9th data item is being
received (before the interrupt is generated), the 9th received data will be written in the
receive FIFO as valid data. To perform transfer properly when the receive overrun interrupt
has been generated, write "1" to the receive overrun interrupt clear register, and then read all
data from the receive FIFO. Even if all the data is not read, data can be transmitted/received
if the receive FIFO has free space and the number of data to be transmitted does not exceed
the free space of the receive FIFO. Note that if the receive FIFO is not read (provided that the
receive FIFO is not empty) within a certain 32-bit period (bit rate) after the receive overrun
interrupt is cleared, a timeout interrupt will be generated.
The above four interrupts combine individual masked sources into a single interrupt. When
any of the above interrupts is asserted, the integrated interrupt INTSSP0 is asserted.
Pre-enable receive overrun interrupt
Pre-enable transmit interrupt
Pre-enable timeout interrupt
Pre-enable receive interrupt
RORIM (mask)
RXIM (mask)
TXIM (mask)
RTIM (mask)
TMPM380/M382 - 5 / 28 -
Post-enable receive overrun interrupt
Post-enable transmit interrupt
Post-enable receive interrupt
Post-enable timeout interrupt
TMPM380/M382
INTSSP0