TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 407

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

14 SSP (Synchronous Serial Port)
14.3 SSP Operation
(1) Initial settings for SSP
(2) SSP enable
(3) Clock ratios
(4) Frame format
Note) When the SSP is in the SPI slave mode and the FSS pin is not used, be sure to transmit data of one byte or
Note) fsys is output from Clock Gear. In details, please refer the chapter of Clock Gear.
Settings for the SSP communication protocol must be made with the SSP disabled.
Control registers SSP0CR0 and SSP0CR1 need to configure this SSP as a master or slave
operating under one of the following protocols. In addition, make the settings related to the
communication speed in the prescale registers SSP0CPSR and SSP0CR0<SCR>.
This SSP supports the following protocols:
• SPI, SSI, Microwire
The transfer operation starts when the operation is enabled with the transmitted data written in
the transmit FIFO, or when transmitted data is written in the transmit FIFO with the operation
enabled.
However, if the transmit FIFO contains only four or fewer entries when the operation is enabled, a
transmit interrupt will be generated. This interrupt can be used to write the initial data.
When setting a frequency for PCLK, the following conditions must be met.
[In master mode]
[In slave mode]
Each frame format is between 4 and 16 bits wide depending on the size of data programmed, and
is transmitted starting from the MSB.
• Serial clock (SP0CLK)
Signals remain LOW in the SSI and Microwire formats and as Inactive in the SPI format while the
SSP is in the idle state. In addition, data is output at the set bit rate only during data transmission.
• Serial frame (SP0FSS)
In the SPI and Microwire frame formats, signals are set to LOW Active and always asserted to
LOW during frame transmission.
In the SSI frame format, signals are asserted only during 1 bit rate before each frame
transmission. In this frame format, output data is transmitted at the rising edge of SP0CLK and
the input data is received at its falling edge.
more in the FIFO before enabling the operation. If the operation is enabled with the transmit FIFO empty, the
transfer data will not be output correctly.
f
f
f
f
In TMPM380, maximum baud-rate is 10Mbps. When system clock is 40MHz, divide by 4)
SP0CLK
SP0CLK
SP0CLK
SP0CLK
(minimum) => fsys / (254 x 256)
(maximum) => fsys / 2 (Note)
(maximum) => fsys / 12
(minimum) => fsys / (254 x 256)
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TMPM380/M382