TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 408

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

• Notes on the Microwire
The Microwire format uses a special master/slave messaging method, which operates in
half-duplex mode. In this mode, when a frame begins, an 8-bit control message is transmitted to
the slave. During this transmit, no incoming data is received by the SSP. After the message has
been transmitted, the slave decodes it, and after waiting one serial clock after the last bit of the
8-bit control message has been sent, it responds with the requested data. The returned data can
be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits.
The details of each frame format are described below:
Note1)
Note2)
(a) SSI frame format
In this mode, the SSP is in idle state, SP0CLK and SP0FSS are forcedly set to LOW, and the
transmit data line SP0DO becomes Hi-Z. When data is written in the transmit FIFO, the
master outputs High pulses of 1 SP0CLK to the SP0FSS line. The transmitted data will be
transferred from the transmit FIFO to the transmit serial shift register. Data of 4 to 16 bits will
be output from the SP0DO pin at the next rising edge of SP0CLK.
Likewise, the received data will be input starting from the MSB to the SP0DI pin at the falling
edge of SP0CLK. The received data will be transferred from the serial shift register into the
receive FIFO at the rising edge of SP0CLK after its LSB data is latched.
SSI frame format (transmission/reception during single transfer)
SP0CLK
SP0FSS
SP0DO
SP0DI
When transmission is disable , SP0DO terminal doesn’t output and is high impedance status. This
terminal needs to add suitable pull-up/down resistance to valid the voltage level.
SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high
impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level.
Hi-Z(Note1)
Hi-Z(Note2)
TMPM380/M382 - 7 / 28 -
MSB
MSB
4 to 16bit
LSB
LSB
Hi-Z(Note2)
Hi-Z(Note1)
TMPM380/M382