TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 41

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

6 Clock/Mode Control
X1
X2
XT1
XT2
Stops oscillation
Starts oscillation
Stops oscillation
fperiph
CGOSCCR
CGOSCCR
CGOSCCR
fsys
after reset.
<XEN2>
after reset
(Note1)
(Note2)
High-speed
oscillator2
High-speed
oscillator1
Low-speed
oscillator
<XTEN>
<XEN1>
after reset
CGOSCCR<WUEON>
CGOSCCR<WUODR13:0>
fs
Warm-up timer
1/2 1/4 1/8 1/16 1/32
The input clocks to selector shown with an arrow are set as default after reset.
OFD can detect oscillation frequency of fosc1 only.
fosc1
fs
fosc2
CGOSCCR
<OSCSEL>
OFD
CGOSCCR <WUPSEL2:1>
fosc
CGOSCCR <PLLON>
PLL Stops after releasing reset
PLL
TMPM380/M382 - 10 / 24 -
Fig. 6-1 Clock Block Diagram
fpll
CGPLLSEL
<PLLSEL>
<PRCK2:0>
CGSYSCR
Starts oscillation after reset
CGSYSCR<FCSTOP>
φT0
1/2
1/2 1/4 1/8 1/16
FCSTOP
<SCOSEL1:0>
CGSYSCR
fc
CGSYSCR <FPSEL0>
<GEAR2:0>
CGSYSCR
fgear
CGCKSEL
<SYSCK>
SCOUT
[Peripheral I/O,
prescaler input]
SSP
[AHB-Bus I/O]
[IO-Bus I/O]
[RTC]
[RMC]
TMRB, MPT, SIO, SBI,
CPU, ROM, RAM,
BOOT ROM, DMAC
TMRB,
RTC, SIO, SBI, I2C,
RMC, ADC, PORT,
Prescaler input
Sampling clock
ADC conversion clock
ADCLK
CGSYSCR<FPSEL1>
TMPM380/M382
MPT,
(To peripheral I/O)
fperiph
WDT,
fsys
fs