TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 411

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

14 SSP (Synchronous Serial Port)
Note1)
Note2)
SP0CLK
SP0FSS
SP0DO
SP0DI
SPI frame format (continuous transfer, <SPO>=0 & <SPH>=0)
With this setting, during the idle period:
• The SP0CLK signal is forcedly set to LOW.
• SP0FSS is forcedly set to HIGH.
• The transmit data line SP0DO is set to LOW.
driven by LOW notifies of the start of transmission. This enables the slave data in the SP0DI
input line of the master.
When a half of the SP0CLK period has passed, valid master data is transferred to the
SP0DO pin. Both the master data and slave data are now set. When another half of SP0CLK
has passed, the SP0CLK master clock pin becomes HIGH. After that, the data is captured at
the rising edge of the SP0CLK signal and transmitted at its falling edge. In the single word
transfer, the SP0FSS line will return to the idle HIGH state when all the bits of that data word
have been transferred, and then one cycle of SP0CLK has passed after the last bit was
captured. However, for continuous transfer, the SP0FSS signal must be pulsed at HIGH
between individual data word transfers. This is because change is not enabled when the
slave selection pin freezes data in its peripheral register and the <SPH> bit is logical 0.
Therefore, to enable writing of serial peripheral data, the master device must drive the
SP0FSS pin of the slave device between individual data transfers. When the continuous
transfer is complete, the SP0FSS pin will return to the idle state when one cycle of SP0CLK
has passed after the last bit is captured.
If the SSP is enabled and valid data exists in the transmit FIFO, the SP0FSS master signal
When transmission is disable , SP0DO terminal doesn’t output and is high impedance status. This
terminal needs to add suitable pull-up/down resistance to valid the voltage level.
SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high
impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level.
LSB
LSB
Hi-Z(Note2)
TMPM380/M382 - 10 / 28 -
MSB
MSB
4 to 16bit
LSB
LSB
Hi-Z(Note2)
MSB
MSB
TMPM380/M382