TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 42

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

6.3.3
6.3.4
(Note)
(Note)
The PLL requires a certain amount of time to be stabilized, which should be secured using the warm-up
function.
for returning from the low power consumption mode triggers the automatic timer count. After the specified
time is reached, the system clock is output and the CPU starts operation.
warm-up time in consideration of the stability time of the PLL and the oscillator.
CGOSCCR<WUEON><WUEF> are used to confirm the start and completion of warm-up timer through
software (instruction). After the completion of warming-up timer is confirmed, switch the system clock by
setting the CGCKSEL<SYSCK>.
CGCKSEL<SYSCKFLG>.
lowers the oscillator input frequency while increasing the internal clock speed.
This circuit outputs the fpll clock that is quadruple of the high-speed oscillator output clock, fosc. This
The PLL is disabled after reset is released. To enable the PLL, set "1" to the CGOSCCR<PLLON> bit.
The warm-up function secures the stability time for the oscillator and the PLL with the warm-up timer.
The warm-up function is also used when returning from STOP/SLEEP mode. In this case, an interrupt
In STOP/SLEEP modes, the PLL is disabled. When returning from these modes, configure the
How to configure the warm-up function
Specify the count up clock for the warm-up timer in the CGOSCCR<WUPSEL 2:1> bits.
The
When clock switching occurs, the current system clock can be checked by monitoring the
Clock Multiplication Circuit (PLL)
Warm-up Function
It takes approx. 200μs for the PLL to be stabilized
warm-up
The warm-up timer operates according to the oscillation clock, and it may contain errors if
there is any fluctuation in the oscillation frequency. Therefore, the warm-up time should be
taken as approximate time.
time
can
be
TMPM380/M382 - 11 / 24
specified
by
setting
the
CGOSCCR<WUODR13:0>.
TMPM380/M382
The