TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 448

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

A master compares the SDA bus line level and the internal SDA output level at the rising of the SCL line. If
there is a difference between these two values, Arbitration Lost occurs and SBInSR <AL> is set to “1”.
15.5.11 Slave Address Match Detection Monitor
15.5.12 General-call Detection Monitor
15.5.13 Last Received Bit Monitor
Master
Master
A
B
Fig 15-13 Example of Master B Lost Arbitration (D7A = D7B, D6A = D6B)
When <AL> is set to “1,” SBInSR <MST, TRX> are cleared to “0,” causing the SBI to
operate as a slave receiver. <AL> is cleared to “0” when data is written to or read from
SBInDBR or data is written to SBInCR2.
When the SBI operates as a slave device in the address recognition mode (SBInI2CAR
<ALS> = ”0”), SBInSR <AAS> is set to “1” on receiving the general-call address or the slave
address that matches the value specified at SBInI2CAR. When <ALS> is “1,” <AAS> is set
to “1” when the first data word has been received. <AAS> is cleared to “0” when data is
written to or read from SBInDBR.
When the SBI operates as a slave device, SBInSR <AD0> is set to “1” when it receives the
general-call address; i.e., the eight bits following the start condition are all zeros. <AD0> is
cleared to “0” when the start or stop condition is detected on the bus.
SBInSR <LRB> is set to the SDA line value that was read at the rising of the SCL line. In the
acknowledgment mode, reading SBInSR <LRB> immediately after generation of the
INTSBIn interrupt request causes ACK signal to be read.
Internal SCL
output
Internal SDA
output
Internal
SCLoutput
Internal SDA
output
Access to SBInDBR or
SBInCR2
<AL>
<MST>
<TRX>
D7A
D7B
TMPM380/M382 - 19 / 41 -
1
1
D6B
D6A
2
2
D5A D4A D3A D2A D1A D0A
3
3
Internal SDA output is fixed to “H”
due to Arbitration Lost of Master B.
4
4
5
Clock output stops here
6
7
8
9
D7A’ D6A’ D5A’ D4A’
1
TMPM380/M382
2
3
4