TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 452

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

SCL
SDA
<PIN>
INTSBIn
interrupt request
(Note) The user can only use a DMA transfer:
Fig 15-14 Generation of the Start Condition and a Slave Address
Slave mode
In the slave mode, the SBI receives the start condition and a slave address.
After receiving the start condition from the master device, the SBI receives a slave
address and a direction bit from the master device during the first eight clocks on the
SCL line. If the received address matches its slave address specified at SBInI2CAR
or is equal to the general-call address, the SBI pulls the SDA line to the “L” level during
the ninth clock and outputs an acknowledgment signal.
The INTSBIn interrupt request is generated on the falling of the ninth clock, and <PIN>
is cleared to “0.” In the slave mode, the SBI holds the SCL line at the “L” level while
<PIN> is “0”.
Start condition
• when there is only one master and only one slave and
• continuous transmission or reception is possible.
A6
1
TMPM380/M382 - 23 / 41 -
A5
2
A4
3
Slave address + Direction bit
A3
4
A2
5
A1
6
A0
7
R/
W
8
TMPM380/M382
Master output
Slave output
ACK
9
Acknowledgement
from slave