TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 466

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

15.7.2 Transfer Modes
The transmit mode, the receive mode or the transmit/receive mode can be selected by
programming SBInCR1 <SIOM1:0>.
Set the control register to the transmit mode and write the transmit data to SBInDBR.
After writing the transmit data, writing “1” to SBInCR1 <SIOS> starts the transmission.
The transmit data is moved from SBInDBR to a shift register and output to the SO pin,
with the least-significant bit (LSB) first, in synchronization with the serial clock. Once the
transmit data is transferred to the shift register, SBInDBR becomes empty, and the
INTSBIn (buffer-empty) interrupt is generated, requesting the next transmit data.
In the internal clock mode, the serial clock will be stopped and automatically enter the
wait state, if next data is not loaded after the 8-bit data has been fully transmitted. The
wait state will be cleared when SBInDBR is loaded with the next transmit data.
In the external clock mode, SBInDBR must be loaded with data before the next data shift
operation is started. Therefore, the data transfer rate varies depending on the maximum
latency between when the interrupt request is generated and when SBInDBR is loaded
with data in the interrupt service program.
At the beginning of transmission, the same value as in the last bit of the previously
transmitted data is output in a period from setting SBInSR <SIOF> to “1” to the falling
edge of SCK.
Transmission can be terminated by clearing <SIOS> to “0” or setting <SIOINH> to “1” in
the INTSBIn interrupt service program. If <SIOS> is cleared, remaining data is output
before transmission ends. The program checks SBInSR <SIOF> to determine whether
transmission has come to an end. <SIOF> is cleared to “0” at the end of transmission. If
<SIOINH> is set to “1,” the transmission is aborted immediately and <SIOF> is cleared
to “0”.
In the external clock mode, <SIOS> must be set to “0” before the next transmit data shift
operation is started. Otherwise, operation will stop after dummy data is transmitted.
INTSBIn interrupt
SBInCR1 ← 0 1 0 0 0 X X X
SBInDBR ← X X X X X X X X
SBInCR1 ← 1 0 0 0 0 X X X
SBInDBR ← X X X X X X X X
8-bit transmit mode
7 6 5 4 3 2 1 0
TMPM380/M382 - 37 / 41 -
Selects the transmit mode.
Writes the transmit data.
Starts transmission.
Writes the transmit data.
TMPM380/M382