TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 488

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

16 Remote control signal preprocessor (RMC)
(4)
<RMCDMAX7:0> bits. If the falling edge of the data bit cycle isn’t monitored after time specified as
threshold in the <RMCDMAX7:0> bits, a maximum data bit cycle is detected. The detection completes
reception and generates an interrupt.
the time of the outbreak of MAX on <RMCEND1> of three RMCEND1 - registers, <RMCEND2>,
<RMCEND3> in data bit period, it occurs by an MAX interrupt in data bit period.
register.
<RMCLL7:0> bits. After the falling edge of the data bit is detected, if the signal stays low longer than
specified, excess low width is detected. The detection completes reception and generates an
interrupt.
To complete data reception, settings of detecting the maximum data bit cycle and excess low width
are required. If multiple factors are specified, reception is completed by the factor detected first.
Make sure to configure the reception completion settings.
1) Completed by a maximum data bit cycle
To complete reception by detecting a maximum data bit cycle, you need to configure the RMCRCR2
To complete reception by setting the number of receive data is set a RMCEND 1 to 3 register
Of each <RMCEND1>、<RMCEND2>、<RMCEND3>.
In this case when the number of set reception bit agreed with the number of bit which I received at
To set the number of receive data can be set in the three RMCEND1>、 <RMCEND2>、 <RMCEND3>
When it can receive the Maximum Data bit , the number of bit is not match the setting value in
<RMCEND1>、<RMCEND2>、<RMCEND3> register., it wait for Leader Reception.
2) Completed by excess low width
To complete reception by detecting the low width, you need to configure the RMCRCR2
Settings of Reception Completion
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TMPM380/M382