TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 521

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

19 Ocsillation Frequency Detector (OFD)
19.3 Control
OFDCR1: 0x4004_0800
Note1) Only "0x06" and "0xF9" is valid to OFDCR1. If other value than "0x06" and "0xF9" is written to
Read/Write
Read/Write
Read/Write
Read/Write
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
(OFDCR2). The detection frequency is specified by lower/higher detection frequency setting registers
(OFDMN, and OFDMX). Writing to OFDCR2, OFDMN, OFDMX, OFDRST is controlled by oscillation
frequency detection control register 1 (OFDCR1).
19.3.1.1
Function
Function
Function
Function
The oscillation frequency detection is controlled by oscillation frequency detection control register 2
OFDCR1, "0x06" is written to OFDCR1 automatically.
OFDWEN7
0x06: Disabling of writing to OFDCR2/OFDMN/OFDMX (Write disable code)
0xF9: Enabling of writing to OFDCR2/OFDMN/OFDMX(Write enable code)
Others: Reserved (Note 1)
Oscillation frequency detection control register1(OFDCR1)
R/W
15
23
31
R
R
R
7
0
0
0
0
-
-
-
OFDWEN6
R/W
14
22
30
R
R
R
6
0
0
0
0
-
-
-
OFDWEN5
TMPM380/382 - 4 / 12 -
R/W
13
21
29
R
R
R
5
0
0
0
0
-
-
-
OFDWEN4
Always read “0”
Always read “0”
Always read “0”
R/W
12
20
28
R
R
R
4
0
0
0
0
-
-
-
OFDWEN3
R/W
11
19
27
R
R
R
3
0
0
0
0
-
-
-
OFDWEN2
R/W
10
18
26
R
R
R
2
1
0
0
0
-
-
-
OFDWEN1
R/W
17
25
1
9
R
R
R
1
0
0
0
-
-
-
TMPM380/382
OFDWEN0
R/W
16
24
0
8
R
R
R
0
0
0
0
-
-
-