TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 557

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

22 DMA Controller (DMAC)
22.4.17 DMACC0Configuration (DMAC Channel0 Configuration Register)
[Explanation]
[31:19]
[18]
[17]
[16]
[15]
[14]
[13:11]
[10]
[9:6]
[5]
[4:1]
[0]
Bit
w. <Halt>
x. <Active>
y. <Lock>
z. <ITC>
Note) Refer to DMA request number chart.
Halts DMA.
Indicates whether data is present in the channel FIFO.
Sets a locked transfer (Non-divided transfer). When locked transfer is enabled, as many burst
transfers as specified are consecutively executed without releasing the bus.
Transfer end interrupt enable
−
ITC
IE
−
−
SrcPeripheral
Halt
Active
Lock
FlowCntrl
DestPeripheral
E
Symbol
Bit
R
R/W
R/W
R/W
R/W
−
R/W
R/W
R/W
−
−
R/W
TMPM380/M382 - 22 / 26 -
Type
Undefined
0y0
0y0
0y0
0y0
0y0
0y000
Undefined
0y000
Undefined
0y000
0y0
Reset
Value
Read undefined. Write as zero.
0y0: Accept a DMA request
0y1: Ignore a DMA request
0y0: No data exists in the FIFO
0y1: Data exists in the FIFO
0y0: Disable locked transfer
0y1: Enable locked transfer
Transfer end interrupt enable register
0y0: Disable interrupt
0y1: Enable interrupt
Error interrupt enable register
0y0: Disable interrupt
0y1: Enable interrupt
0y100~0y111: Reserved
Read undefined. Write as zero.
Transfer destination peripheral (Note 1)
0y000∼0y1111
Read undefined. Write as zero.
Transfer source peripheral (Note 1)
0y000∼0y1111
Channel enable
0y0 : Disable
0y1 : Enable
0y000
0y001
0y010
0y011
setting value
FlowCntrl
Address = (0x4008_0000) + 0x0110
Memory to Memory
Memory to Peripheral
Peripheral to Memory
Reserved
Description
Transfer method
TMPM380/M382