TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 559

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

22 DMA Controller (DMAC)
22.5 Special Functions
22.5.1 Scatter/gather function
When removing a part of image data and transferring it, image data cannot be handled as
consecutive data, and the address changes dramatically depending on the special rule. Since
DMA can transfer data only by using consecutive addresses, it is necessary to make required
settings at locations where addresses changes.
The scatter/gather function can consecutively operate DMA settings (transfer source address,
destination address, number of transfers, and transfer bus width) by re-loading them each time a
specified number of DMA executions have completed via a pre-set "Linked List" where the CPU
does not need to control the operation.
Setting "1" in the DMACCxLLI register enables/disables the operation.
The items that can be set with Linked List are configured with the following 4 words:
They can be used with the interrupt operation.
An interrupt depends on the Terminal Count Interrupt enable bit of the DMACCxControl register,
and can be generated at the end of each LLI. When this bit is used, a condition can be added
even during transfer using LLI to perform branch operation, etc. To clear the interrupt, control the
appropriate bit of the DMACIntTCClear register.
1) DMACCxSrcAddr
2) DMACCxDestAddr
3) DMACCxLLI
4) DMACCxControl
Screen image
TMPM380/M382 - 24 / 26 -
Remove a part of
the screen image
Screen data
Addresses are not
successive
TMPM380/M382