TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 589

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

23 Flash Memory Operation
1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer
2. The 3rd byte, which the target board receives from the controller, is a command. The
3. The 4th byte, transmitted from the target board to the controller, is an acknowledge
4. The 5th byte, transmitted from the target board to the controller, is the Chip Erase
5. The 6th byte, transmitted from the target board to the controller, is an acknowledge
code for the Show Product Information command is 0x40.
response to the 3rd byte. Before sending back the acknowledge response, the boot
program checks for a receive error. If there was a receive error, the boot program
transmits x8H (bit 3) and returns to the command wait state again. In this case, the
upper four bits of the acknowledge response are undefined - they hold the same
values as the upper four bits of the previously issued command.
Enable command code (0x54).
2)
command.
If the 3rd byte is equal to any of the command codes listed in Table 23-4 , the boot
program echoes it back to the controller. When the Show Flash Memory Sum
command was received, the boot program echoes back a value of 0x40. If the 3rd byte
is not a valid command, the boot program sends back 0xN1 (bit 0) to the controller and
returns to the state in which it waits for a command (the third byte) again. In this case,
the upper four bits of the acknowledge response are undefined - they hold the same
values as the upper four bits of the previously issued command.
response to the 5th byte.
Before sending back the acknowledge response, the boot program checks for a
receive error. If there was a receive error, the boot program transmits 0xN8 (bit 3) and
returns to the command wait state again. In this case, the upper four bits of the
acknowledge response are undefined - they hold the same values as the upper four
bits of the previously issued command.
If the 5th byte is equal to any of the command codes to enable erasing, the boot
program echoes it back to the controller. When the Show Flash Memory Sum
command was received, the boot program echoes back a value of 0x54 and then
branches to the Chip Erase routine. If the 5th byte is not a valid command, the boot
program sends back 0xN1 (bit 0) to the controller and returns to the state in which it
waits for a command (the third byte) again. In this case, the upper four bits of the
acknowledge response are undefined - they hold the same values as the upper four
bits of the previously issued command.
Chip and Protection Bit Erase command (See Table 23-7)
TMPM380/M382 - 28 / 54 -
TMPM380/M382