TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 604

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

4) Automatic programming of protection bits (for each block)
(Note) Software reset is ineffective in the seventh bus write cycle of the automatic
This device is implemented with protection bits. This protection can be set for each block.
See Table 23-18 for table of protection bit addresses. This device assigns 1 bit to 1 block as
a protection bit. The applicable protection bit is specified by PBA in the seventh bus write
cycle. By automatically programming the protection bits, write and/or erase functions can be
inhibited (for protection) individually for each block. The protection status of each block can
be checked by the FLCS <BLPRO> register to be described later. This status of the
automatic programming operation to set protection bits can be checked by monitoring FLCS
<RDY/BSY> (See Table 23-13). Any new command sequence is not accepted while
automatic programming is in progress to program the protection bits. If it is desired to stop
the programming operation, use the hardware reset function. In this case, it is necessary to
perform the programming operation again because the protection bits may not have been
correctly programmed. If all the protection bits have been programmed, all the FLCS
<BLPRO> bits are set to "1" indicating that it is in the protected state (See Table 23-13 ).
This disables subsequent writing and erasing of all blocks.
has not been normally terminated.
Also, any protected blocks cannot be erased. If an automatic block erase operation has
failed, the flash memory is locked in the mode and will not return to the read mode. In this
case, execute hardware reset to reset the device.
protection bit programming command. The FLCS <RDY/BSY> bit turns to
"0" after entering the seventh bus write cycle.
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