TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 610

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

Address
Normal
commands
ID
-READ
Block erase
Auto page
programming
Protection bit
programming
Protection bit
erase
Block erase
(Note 1)
(Note 3)
(Note 2)
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
(7)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
Flash area
Flash area
Flash area
Flash area
[31:19]
Addr
Table 23-15”Operation Modes” can also be used.
Address setting can be performed according to the "Normal bus write cycle address
configuration" from the first bus cycle.
"0" is recommended" can be changed as necessary.
Block selection (Table 23-17)
Block selection (Table 23-17)
BA: Block address (Set the sixth bus write cycle address for block erase operation)
BA: Block address (Set the sixth bus write cycle address for block erase operation)
Address bit configuration for bus write cycles
IA: ID address (Set the fourth bus write cycle address for ID-Read operation)
Table 23-16 Address Bit Configuration for Bus Write Cycles
Protection bit selection
Addr
Protection bit
(Table 23-19)
[18]
“0” is recommended.
“0” is recommended.
selection
(Table 23-18)
Addr
[17]
Normal bus write cycle address configuration
Addr
TMPM380/M382 - 49 / 54 -
[16]
Page selection
Addr
[15]
ID address
“0” is recommended.
Addr
[14]
Fixed to “0”.
[13:11]
Addr
Addr[1:0]=“0” (fixed) , Others:0 (recommended)
Addr[1:0]=“0” (fixed) , Others:0 (recommended)
Command
Addr[1:0]=“0” (fixed) , Others:0 (recommended)
(Table 23-18)
Addr
Protection bit
Protection bit
(Table 23-19)
[10]
selection
selection
Addr
[9]
Addr
[8]
Others:0 (recommended)
Others:0 (recommended)
Others:0 (recommended)
TMPM380/M382
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
(recommended)
Others:0
[7:0]
Addr