TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 680

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

SCL clock frequency
Hold time for START condition
SCL low width (Input) (Note 1)
SCL high width (Input) (Note 2)
Setup time for a repeated START
condition
Data hold time (Input) (Note 3, 4)
Data setup time
Setup time for a stop condition
Bus free time between stop condition
and start condition
(Note 2) SCL clock high width (output) is calculated with: (2
(Note 3) The output data hold time is equal to 12x of internal SCL.
(Note 4) The Philips I2C-bus specification states that a device must internally provide a hold time of at least
(Note 5) Software-dependent.
(Note 6) The Philips I2C-bus specification instructs that if the power supply to a Fast-mode device is switched
(1) I2C Mode
(Note 1) SCL clock low width (output) is calculated with: (2
Notice: On I2C-bus specification, Maximum Speed of Standard Mode is 100KHz, Fast mode is
400KHz. Internal SCL Frequency setting should comply with Note1 & Note2 shown above.
27.6.3 Serial Bus Interface（I2C/SIO）
fsys cycle time. It varies depending on the programming of the clock gear function.
SBInCR.
SDA
SCL
300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. However, this SBI
does not satisfy this requirement. Also, the output buffer for SCL does not incorporate slope control of
the falling edges; therefore, the equipment manufacturer should design so that the input data hold
time shown in the table is satisfied, including tr/tf of the SCL and SDA lines.
off, the SDA and SCL I/O pins must be floating so that they don’t obstruct the bus lines. However, this
SBI does not satisfy this requirement.
Parameter
In the table below, the letter x represents the I2C operation clock cycle time which is identical to the
n denotes the value of n programmed into the SCK (SCL output frequency select) field in the
S: Start condition
Sr: Repeated start condition
P: Stop condition
S
t
HD;STA
t
f
t
LOW
t
SU;DAT
t
SCL
t
t
t
t
t
t
t
t
t
Symbol
SCL
HD:STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
t
r
t
HIGH
(Note 5)
(Note 5)
Min
0
-
-
-
-
-
-
t
Equation
HD;DAT
TMPM380/M382 - 7 / 21 -
Max
-
-
-
-
-
-
-
-
-
n-1
n-1
Standard Mode
Min
250
4.0
4.7
4.0
4.7
0.0
4.0
4.7
t
0
+58)/x
SU;STA
+12)/x
Sr
Max
100
-
-
-
-
-
-
-
-
t
SU;STO
Min
100
0.6
1.3
0.6
0.6
0.0
0.6
1.3
P
0
Fast Mode
t
BUF
Max
400
TMPM380/M382
-
-
-
-
-
-
-
-
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs