TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 75

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

7 Exceptions
(6) Enabling interrupt by CPU
enable the intended interrupt with the Interrupt Set-Enable register. Each bit of the register is assigned to
each interrupt factor.
Writing “1” to the corresponding bit of the Set-Enable register enables the intended interrupt.
specified in the clock generator, and notified to the CPU.
detection. However, if “H” or “L” level signal is specified as the trigger to enter the active state, the CPU
considers that the interrupt factor is cleared upon exiting from the active state. Therefore, the active state
needs to be kept until the interrupt is detected.
the interrupt signal as an interrupt factor when it is changed from “L” to “H”. To generate an interrupt again,
the factor held in the clock generator needs to be cleared with the CGICRCG clear register.
before entering the interrupt service routine.
7.5.2.3 Detection by Clock Generator
7.5.2.4 Detection by CPU
7.5.2.5 CPU processing
Enable the interrupt by the CPU as shown below.
It is possible to clear the suspended interrupt by writing the Interrupt Clear-Pending register. Then,
Writing “1” to the corresponding bit of the Clear-Pending register clears the suspended interrupt.
If the interrupt is used for clearing the standby mode, the interrupt factor is detected by an active level
The interrupt active level triggered by a rising or falling edge is kept in the clock generator after
The clock generator notified to the CPU the interrupt detected by “H” level signal. The CPU considers
The CPU detects an interrupt factor with the highest priority.
On detecting the interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack
(Note)
●CPU register
Interrupt Clear-Pending<m>
Interrupt Set-Enable<m>
m: corresponding bit
TMPM380/M382 - 20 / 59 -
←
←
“1”
“1”
TMPM380/M382