TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 195
TMP92xy22FG
Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY22FG.pdf
(260 pages)
Specifications of TMP92xy22FG
Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
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SCK pin
SO pin
Shift register
SCK pin
SI pin
Shift register
2.
Leading edge shift
Trailing edge shift
* : Don’t care
Shift edge
edge.
SCK pin input/output).
SCK pin input/output).
Data is transmitted on the leading edge of the clock and received on the trailing
Data is shifted on the leading edge of the serial clock (on the falling edge of the
Data is shifted on the trailing edge of the serial clock (on the rising edge of the
********
76543210 * 7654321 ** 765432 *** 76543 **** 7654 ***** 765 ****** 76
Bit0
Bit0
7 ******* 76 ****** 765 ***** 7654 **** 76543 *** 765432 ** 7654321 * 76543210
Bit1
Bit1
Figure 3.10.24 Shift Edge
92CM22-193
Bit2
Bit2
(a) Leading shift
(b) Trailing shift
Bit3
Bit3
Bit4
Bit4
Bit5
Bit5
Bit6
Bit6
******* 7
Bit7
Bit7
TMP92CM22
2007-02-16
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