TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 102

no-image

TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
Note: Since an interrupt is generated 80 times, the first read to internal RAM (which requires 1 additional state) occurs
Sample 1: Calculation example for CPU + HDMA
Conditions:
Calculation example:
Transfer count
80 times, requiring additional 80 states in total. In addition, from bus REQ to bus ACK, an overhead time of 2
states is also needed for each interrupt request, requiring additional 160 states in total.
follows:
16 (64 bytes/4 bytes = 16 times) and counter B is set to 80.
CPU operation speed (f
I2S sampling frequency : 48 KHz (60 MHz/25/50 = 48 KHz)
I2S data transfer bit length
DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I2S
DMAC source data read time:
DMAC destination write time:
To transfer 5 Kbytes of data in 4-byte units, the transfer count is calculated as
5 Kbytes/4 bytes = 1280 [times]
Since I2S generates an interrupt for every 64 bytes, the DMAC’s counter A is set to
t
HDMA start interval [s] = 1 / I2S sampling frequency [Hz] × (64 / 16 )
CPU bus stop rate = t
STOP
Internal RAM data read time
= 1 state/4 bytes (However, the first 1 byte requires 2 states.)
I2S register write time = 2 states/4 bytes
(HDMA) = (((1 + 2) × 16) × 80) + 80 + 160) / f
STOP
SYS
92CF26A-100
= 68 [μS] / 83.33 [mS] = 0.08 [%]
)
(HDMA) [s] / HDMA start interval [s]
: 60 MHz
: 16 bits
= 83.33 [mS]
SYS
[S] = 68 [μS]
TMP92CF26A
2009-06-25

Related parts for TMP92xy26AXBG