TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 106

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Sample3: Calculation example for CPU + LDMA + ARDMA
Conditions:
Calculation example:
CPU operating speed (f
t
Since SDRAM is auto-refreshed once or less in 5.47 [μs]:
t
CPU bus stop rate
STOP
STOP
(LDMA)
(ARDMA)
Display RAM
Display size
Display quality
Refresh rate
SDRAM auto refresh
LHSYNC [period:s]
SYS
92CF26A-104
=((SegNum × K / 8) × t
= 2 / f
= t
)
STOP
SYS
(LDMA･ARDMA) [s] / LHSYNC [period:s]
: 60 MHz
: 16-bit external SDRAM
: QVGA (320seg × 240com)
: 65536 colors (TFT)
: 70 Hz (including 20 clocks of dummy cycles)
: Every 936 states (15.6 μs)
= ((320 ×16 / 8) × 1 / f
= ((640) × 16.67 [ns] / 2) + 133.33 [ns]
= 5.47 [μs]
= 1/70 [Hz] / (COM + 20 = 260) = 54.95 [μs]
= (5.47 [μs] + 33.33 [ns]) / 54.95 [μs] = 10.01 [%]
[Hz] = 33.33 [ns]
LRD
) + (8 / f
SYS
SYS
[Hz] / 2) + (8 / f
[Hz])
TMP92CF26A
2009-06-25
SYS
[Hz])