TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 108

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Sample 4: Calculation example for CPU + LDMA+ ARDMA + HDMA
Conditions:
Calculation example:
possible.
calculated as follows:
time (maximum HDMA time) must be set to 30.92 [μS] or less. Although transferring
all 5 Kbytes from the internal RAM to I2S requires t
maximum HDMA time should be limited by using the HDMATR register.
CPU operation speed (f
Display RAM
Display quality
Refresh rate
SDRAM Auto Refresh
SDRAM
HDMA
t
LHSYNC [period: s] = 1/70 [Hz] /(COM+20 = 260) = 54.95 [μs]
t
LCD driver data transfer time [s]
Since LHSYNC [period: s] < LCD driver data transfer time [s], this setting is not
When the transfer speed is changed to x4, the LCD driver data transfer time is
(The transfer speed should be adjusted according to the required specifications.)
LHSYNC [period: s] − LCD driver data transfer time [s] − t
To realize proper LCD display, the maximum time HDMA can occupy the bus at a
STOP
STOP
(LDMA) =((SegNum × K / 8) × tLRD) + (1 / f
(HDMA) = (((1 + 2) × 16) × 80) + 80 + 160) / f
LCD driver data transfer time [s]
: Transfers 5 Kbytes from internal RAM to I2S
SYS
92CF26A-106
: QVGA (320seg × 240com)
: 65536 colors (TFT)
: 70 Hz (including 20 clocks of dummy cycles)
: Every 936 states (15.6 μs)
: 16-bit width
= ((320 ×16 / 8) × 1 / f
= ((640) ×16.67 [ns] / 4) + 16.67 [ns]
= 2.68 [μs]
= SegNum × (1/ f
= 320 × (1/60 MHz) × 16 = 85 [μs]
= SegNum × (1/ f
= 320 × (1 / 60MHz) × 4 = 21.3 [μs]
= 54.95 [μs] − 21.3 [μs] − 2.68 [μs] = 30.94 [μs]
)
: 60 MHz
SYS
SYS
) × (LD bus transfer speed)
) × (LD bus transfer speed)
SYS
[Hz] / 4) + (1 / f
SYS
SYS
STOP
[Hz])
[s] = 68 [μs]
STOP
(HDMA) = 68 [μs], the
(LDMA)
SYS
TMP92CF26A
[Hz])
2009-06-25