TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 11

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PF0
I2S0CKO
PF1
I2S0DO
PF2
I2S0WS
PF3
I2S0WS
PF4
I2S1CKO
PF5
I2S1WS
PF7
SDCLK
PG0 to PG1
AN0 to AN1
PG2
AN2
MX
PG3
AN3
MY
PG4 to PG5
AN4 to AN5
PJ0
PJ1
PJ2
PJ3
SDLLDQM
PJ4
SDLUDQM
PJ5
NDALE
PJ6
NDCLE
PJ7
SDCKE
SDRAS
SRLLB
SRLUB
SDWE
SRWR
ADTRG
SDCAS
Pin name
Number
of Pins
1
1
1
1
1
1
1
2
1
1
2
1
1
1
1
1
1
1
1
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 2.2.1 Pin names and functions (3/6)
Port F0: I/O port
Outputs clock for I
Port F1: I/O port
Outputs data for I
Port F2: I/O port
Outputs word select signal for I
Port F3: I/O port
Outputs clock for I
Port F4: I/O port
Outputs data for I
Port F5: I/O port
Outputs word select signal for I
Port F7: Output port
Clock for SDRAM
Port G0 to G1: Input port
Analog input pin 0 to 1: Input pin for AD converter
Port G2: Input port
Analog input pin 2: Input pin for AD converter
X-Minus: Pin connected to X- pin for Touch Screen I/F
Port G3: Input port
Analog input pin 3: Input pin for A/D converter
Y-Minus: Pin connected to Y- pin for Touch Screen I/F
A/D Trigger: Request signal for A/D start
Port G4 to G5: Input port
Analog input pin 4 to 5: Input pin for A/D converter
Port J0: Output port
Outputs strobe signal for SDRAM row address
Data enable signal for D0 to D7 for SRAM
Port J3: Output port
Data enable signal for D0 to D7 for SDRAM
Port J4: Output port
Data enable signal for D8 to D15 for SDRAM
Port J5: I/O port
Address latch enable signal for NAND Flash
Port J6: I/O port
Command latch enable signal for NAND Flash
Port J7: Output port
Clock enable signal for SDRAM
Port J1: Output port
Outputs strobe signal for SDRAM column address
Data enable signal for D8 to D15 for SRAM
Port J2: Output port
Outputs write enable signal for SDRAM
Write enable for SRAM: Outputs strobe signal to write data
92CF26A-9
2
2
2
S0
2
S1
S0
S1
2
2
S0
S1
Functions
TMP92CF26A
2009-06-25