TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 127

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

P7
(001CH)
P7CR
(001EH)
P7FC
(001FH)
P7DR
(0087H)
P73 setting
P76 setting
<P76F>
<P73F>
<
<P73C>
<P76C>
0
1
0
1
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: A read-modify-write operation cannot be performed for P7CR, P7FC.
Note2: When NDRE and NDWE are used, set registers in the following order to avoid outputting a negative glitch.
Note3: It is set to “Port” or “Data bus” by AM pins state.
WAIT
Input Port
Input Port
Reserved
0
0
Input
Order
(1)
(2)
(3)
------------------------------------------------------
EA24Output
Output Port
Output Port
Reserved
7
7
7
7
1
1
Registser
P7
P7FC
P7CR
(Output latch register is
0:Port
1: WAIT
Data from external port
P76C
P76D
P76F
P76
6
6
6
6
0
−
0
−
1
−
P72 setting
P75 setting
<P72F>
<P75F>
set to “1”)
<
bit2
0
1
1
Figure 3.7.11 Register for Port 7
<P72C>
<P75C>
0
1
0
1
−
Port 7 Function register
Port 7 Control register
P75C
P75F
P75D
P75
Port 7 Drive register
5
5
0
−
5
−
5
0
1
−
Input/Output buffer drive register for standby mode
NDR/
92CF26A-125
Refer to following table
Input Port
Reserved
Input Port
Port 7 register
bit1
0
1
1
0
B
0
(Output latch register is
Input R/W Output
Data from external port
0: Input 1: Output
P74C
P74F
P74D
P74
4
cleared to “0”)
4
4
−
0
−
0
4
−
1
(at <P72>=0)
NDWE
WRLU
(at <P72>=1)
Output Port
Output Port
W
1
−
Output
1
Output
P73C
P73F
P73D
R/W
P73
R/W
3
3
3
W
−
0
−
3
−
0
1
P74 setting
P71 setting
<P74F>
<P71F>
0:Port
1:
at
<P72> = 0
<P72> = 1
(Output latch register is
WRLU
Data from external port
<P71C>
P72C
P72F
NDWE
P72D
<P74C>
0
1
0
1
P72
2
2
2
−
0
−
2
0
1
−
at
set to “1”)
−
Input Port
Reserved
Input Port
Reserved
0:Port
1:
<P71> = 0
<P71> = 1
NDRE
WRLL
0
P71C
P71F
P71D
0
P71
1
1
1
0
−
0
−
1
−
1
at
at
(at <P71>=0)
(at <P71>=1)
NDRE
WRLL
Output Port
EA25Output
Output Port
0:Port
1:
0/1 Note3:
TMP92CF26A
Output
1
Output
RD
P70D
P70F
P70
1
0
−
0
0
−
0
1
1
−
2009-06-25