TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 128

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.7.6
output latches of P80 to P81, P83 to P87 to “1”. But if it is started at boot mode (AM [1:0]=
“11”), output latch of P82 is set to “1”.
register P8FC.
functions.
Port 8 (P80 to P87)
Ports 80 to 87 are 8-bit output ports. Resetting sets the output latch of P82 to “0” and the
Port 8 can also be set to function as an interface-pin for external memory using function
Writing “1” in the corresponding bit of P8FC and P8FC2 enables the respective
Resetting P8FC to “0” and P8FC2 to “0”, sets all bits to output ports.
Reset
Output latch
P8FC write
P8FC2 write
Function
Function
control2
P8 write
control
P8 read
CS ,
Figure 3.7.12 Port 8
“1”, SDCS , CSZA , CSXA ,“1”, “1”, “1”, “1”
0
CS
92CF26A-126
CS ,
0
Selector
1
,
SDCS
CS ,
S
2
,
CS , CSZB , CSZC , CSZD , CSXB
SDCS
3
,
CSXA
,
CSZB
,
CSZC
P80 (
P81 (
P82 (
P83 (
P84 ( CSZB )
P85 ( CSZC )
P86 ( CSZD ,
P87 ( CSXB ,
,
CS )
CS , SDCS )
CS , CSZA , SDCS )
CS , CSXA )
ND
1
0
2
3
0
CE
ND
ND
,
ND
0
1
CE
CE
1
CE
)
)
TMP92CF26A
2009-06-25