TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 129

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

P8
(0020H)
P8FC
(0023H)
P8DR
(0088H)
P87 setting
P8FC2
(0021H)
P86 setting
<P87F2>
<P86F2>
<P87F>
0
1
0
1
<P86F>
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: A read-modify-write operation cannot be performed for P8FC and P8FC2.
Note2: Do not write “1” to P8<P82> register before setting P82-pin to
Note3: If it is started at boot mode (AM [1:0] = “11”), output latch of P82 is set to “1”.
Note4: When
Don’t setting
Output port
Output port
setting
Don’t
0
0
outputs “0” as CE for program memory.
Order
------------------------------------------------------
(1)
(2)
(3)
0: Port
1: <P87F2>
0:
1:
ND
CSXB
P87F2
P87D
P87F
ND
P87
CSXB Output
1
ND
7
7
7
7
1
−
0
−
0
−
CE
1
−
Output
Output
CSZD
ND
1
CE
1
0
CE
0
Registser bit2
P8
P8FC2
P8FC
1
CE
Output
W
0: Port
1: <P86F2>
0:
1:
and
P86F2
P86D
P86F
CSZD
ND
P86
6
1
−
6
6
6
0
−
0
−
1
−
P83 setting
<P83F2>
0
ND
CE
Figure 3.7.13 Register for Port 8
1
1
1
1
CE
<P83F>
0
1
Input/Output buffer drive register for standby mode
Port 8 Function registers 2
0: Port
1:
are used, set registers by following order.
Port 8 Function register
P85F
P85D
P85
CSZC
Port 8 Drive register
5
5
1
−
0
−
5
5
1
−
92CF26A-127
Port 8 register
bit1
1
1
1
Output
port
0
0: Port
1:
CSXA Output
CSZB
P84F
P84D
P84
4
4
0
−
1
−
4
4
1
−
R/W
Output
R/W
CS
W
1
Refer to following table 0: Port
Refer to following table
3
P83F2
P83D
P83F
P83
3
3
3
3
1
−
0
−
0
−
1
−
CS
P82 setting
<P82F2>
0 (Note3)
2
P82F2
P82F
P82D
<P82F>
P82
0
1
or CSZA because, on reset, P82-pin
2
W
−
2
2
2
0
−
0
−
1
−
Output port
1:
0: <P81F>
1:
Output
CSZA
P81F2
P81D
P81F
P81
CS
SDCS
0
1
1
1
−
1
1
0
−
0
−
1
−
1
0: Port
1:
CS
TMP92CF26A
P80D
Output
P80F
2
SDCS
P80
CS
0
1
−
0
0
0
1
−
0
−
1
2009-06-25
Output
0