TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 138

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PC5 setting
PCDR
(008CH)
<PC5F>
<PC2F>
PC2 setting
PCCR
(0032H)
PC
(0030H)
PCFC
(0033H)
<PC5C>
<PC2C>
0
1
0
1
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Input port
Input port
output
EA27
INT2
Note 1: A read-modify-write operation cannot be performed for the registers PCCR, PCFC.
Note 2: When setting PC3-PC0 pins to INT3-INT0 input, set PCDR<PC3D: PC0D> to “0000”(prohibit input), and
0
0
when driving PC3-PC0 pins to “0”, execute HALT instruction. This setting generates INT3-INT0 inside. If don’t
use external interrupt in HALT condition, set like an interrupt don’t generated. (e.g. change port setting)
Don’t setting
Output port
Output port
Reserved
PC7D
PC7C
PC7F
PC7
1
1
7
7
7
7
0
−
0
−
1
−
PC6C
PC6D
PC6F
PC7 setting
PC4 setting
PC1 setting
PC6
<PC4F>
<PC1F>
<PC7F>
6
6
6
0
−
6
1
−
0
−
Figure 3.7.24 Register for Port C
<PC4C>
<PC1C>
<PC7C>
Data from external port (Output latch register is set to “1”)
0
1
0
1
0
1
Input/Output buffer drive register for standby mode
Port C function register
Port C control register
PC5C
PC5D
PC5F
PC5
Port C drive register
5
5
5
5
0
0
−
1
−
Input port
−
Input port
Input port
92CF26A-136
output
setting
EA26
Port C register
Don’t
INT1
0
0
0
Refer to following table
PC4C
PC4D
PC4F
0: Input 1: Output
PC4
0
−
4
4
4
4
KO8output
(Open-drain)
0
−
1
−
TA0IN input
Output port
Output port
Output port
Reserved
R/W
R/W
1
W
W
1
1
−
PC3C
PC3F
PC3D
PC3
3
3
0
−
3
0
−
3
1
−
PC3 setting
<PC0F>
<PC3F>
PC6 setting
<PC6F>
PC0 setting
<PC3C>
<PC6C>
<PC0C>
0
1
PC2C
PC2F
PC2D
0
1
0
1
PC2
2
2
2
0
−
0
−
2
1
−
Input port
Input port
Input port
output
EA28
INT3
INT0
PC1C
0
0
PC1F
PC1D
0
PC1
0
−
1
1
1
0
−
1
1
−
Don’t setting
TA2IN input
Output port
Output port
Output port
Reserved
TMP92CF26A
PC0C
PC0F
PC0D
PC0
1
1
1
0
0
0
−
0
0
−
0
1
−
2009-06-25