TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 144

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
PGDR
(0090H)
PGFC
(0043H)
PG
(0040H)
Bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note: The input channel selection of the AD converter and the permission of for ADTRG input are set by AD
Note 1: A read-modify-write operation cannot be performed for the registers PGFC.
Note 2: PG register is prohibited to access by byte. All the instruction (Arithmetic/ Logical/ Bit operation and rotate/
Note 3: Don’t use PG register at the state that mingles Analog input and Digital input.
converter mode register ADMOD1.
shift instruction) access by byte are prohibited. Word access is always needed.
Example: LD
7
7
7
6
6
6
Figure 3.7.30 Register for Port G
wa, (PG)
Port G Function register
Port G driver register
PG5
5
5
5
92CF26A-142
Port G register
: Using only “a” register data, and cancel “w” register data.
PG4
4
4
4
Data from external port
0: Input port
1:
or AN3
ADTRG
PG3D
Input/Output buffer
PG3F
PG3
drive register for
3
3
standby mode
W
3
1
0
R/W
R
PG2D
PG2
2
2
1
2
PG1
1
1
1
TMP92CF26A
PG0
0
0
0
2009-06-25

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