TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 145

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.7.12
they output “1”. PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as a
port, Port J also functions as output pins for SDRAM (
SDLUDQM, and SDCKE), SRAM (
and NDCLE).
automatically according to the setting of the memory controller.
Port J (PJ0 to PJ7)
PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to “1”, and
The above settings are made using the function register PJFC.
However, either SDRAM or SRAM output signal for PJ0 to PJ2 are selected
Reset
(on bit basis)
(on bit basis)
PJFC write
PJFC2 write
Function
Function
Selector
control2
PJ write
control
PJ read
Figure 3.7.31 Port J0 to J4 and J7
92CF26A-143
SRLLB , SRLUB , SRWR
SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDCKE
Selector
SRWR
S
,
SRLLB
and
SDRAS
PJ0(
PJ1 (
PJ2(
PJ3(SDLLDQM)
PJ4(SDLUDQM)
PJ7(SDCKE)
SRLUB
SDRAS
SDWE
SDCAS
,
) and NAND-Flash(NDALE
SDCAS
,
,
SRWR
,
SRLLB
SRLUB
)
,
)
SDWE
)
TMP92CF26A
, SDLLDQM,
2009-06-25