TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 150

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

TMP92CF26A
3.7.14
Port L (PL0 to PL7)
PL0 to PL7 are 8-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to
PL7 pins output “0”. In addition to functioning as a general-purpose output port, port L can
also function as a data bus for an LCD controller (LD0 to LD7). The above settings are
made using the function register PLFC.
Reset
Function
control
PLFC write
R
Output latch
S
A
Selector
PL0 to PL7
PL write
(LD0 to LD7)
B
LD0 to LD7
PL read
Figure 3.7.36 Port L0 to L7
2009-06-25
92CF26A-148