TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 155

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
3.7.16
or output. Resetting sets Port N to an input port.
key-board interface pin (KO0 to KO7) which can be set to open-drain output buffer.
Port N (PN0 to PN7)
PN0 to PN7 are 8-bit general-purpose I/O port. Each bit can be set individually for input
In addition to functioning as a general-purpose I/O port, Port N can also function as
Output latch
PN write
S
Reset
(on bit basis)
(on bit basis)
Direction
Function
control
control
PNFC write
PNCR write
PC read
Figure 3.7.42 Port N
92CF26A-153
Selector
S
A
B
Open-drain
enable
PN0(KO0) to PN7(KO7)
TMP92CF26A
2009-06-25

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