TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 156

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PN
(005CH)
PNCR
(005EH)
PNFC
(005FH)
PNDR
(0097H)
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note : A read-modify-write operation cannot be performed for the registers PNCR and PNFC.
PN7C
PN7D
PN7F
PN7
7
7
7
7
0
−
0
−
1
−
PN6C
PN6D
PN6F
PN6
6
6
6
6
0
−
0
−
1
−
Figure 3.7.43 Register for Port N
Data from external port (Output latch register is set to “1”)
Input/Output buffer drive register for standby mode
Port N control register
Port N function register
PN5C
PN5D
PN5F
PN5
Port N drive register
0
−
1
−
5
5
5
0: CMOS output 1: Open-drain output
5
0
−
92CF26A-154
Port N register
0: Input
PN4C
PN4D
PN4F
PN4
−
0
4
4
0
−
4
4
1
−
R/W
R/W
W
W
−
1: Output
PN3C
PN3D
PN3F
PN3
−
−
3
3
0
3
0
3
1
−
PN2C
PN2D
PN2F
PN2
2
2
2
2
−
0
−
0
−
1
PN1C
PN1D
PN1F
PN1
1
1
1
1
1
−
0
−
0
−
TMP92CF26A
PN0C
PN0D
PN0F
PN0
−
0
0
0
0
1
0
−
0
−
2009-06-25