TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 163

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PR
(0064H)
PRCR
(0066H)
PRFC
(0067H)
PRDR
(0099H)
PR3setting
PR1 setting
<PR1F>
<PR3F>
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
<PR1C>
<PR3C>
0
1
0
1
Note: A read-modify-write operation cannot be performed for the registers PRCR, PRFC.
Reserved
Reserved
Input port
Input port
0
0
7
7
7
7
Output port
Output port
SPCLK
SPDO
output
output
1
1
Figure 3.7.51 Register for Port R
6
6
6
6
PR2 setting
PR0 setting
<PR0F>
<PR2F>
Port R function register
Port R control register
Port R drive register
<PR0C>
<PR2C>
5
5
5
5
0
1
0
1
92CF26A-161
Port R register
SPDI input
Input port
Input port
Reserved
4
4
4
4
0
0
0: Port
1: SPCLK
PR3C
Output port
PR3F
PR3D
Output port
PR3
Reserved
3
3
3
−
3
−
0
−
0
1
Output
(Output latch register is cleared to “0”)
SPCS
1
1
Input/Output buffer drive register
0: Port
1: SPCS
Data from external port
PR2C
PR2F
PR2D
0: Input, 1: Output
PR2
for standby mode
2
2
2
1
−
0
−
0
−
2
R/W
R/W
W
W
−
0: Port
1: SPDO
PR1C
PR1D
PR1F
PR1
1
1
−
1
−
1
1
−
0
0
0: Port
1: SPDI
TMP92CF26A
PR0C
PR0F
PR0D
PR0
0
0
0
−
0
−
0
0
1
−
2009-06-25